Download e-book for iPad: Fine- and Coarse-Grain Reconfigurable Computing by Stamatis Vassiliadis, Dimitrios Soudris, Y. Patt, J. Smith,

By Stamatis Vassiliadis, Dimitrios Soudris, Y. Patt, J. Smith, M. Valero

ISBN-10: 1402065043

ISBN-13: 9781402065040

ISBN-10: 1402065051

ISBN-13: 9781402065057

The elemental options and construction blocks for the layout of excellent- (or FPGA) and Coarse-Grain Reconfigurable Architectures are mentioned during this e-book. Recently-developed built-in structure layout and software-supported layout circulation of FPGA and coarse-grain reconfigurable structure also are defined. The ebook is followed through an interactive CD including case reports and lab initiatives for the layout of FPGA and Coarse-grain architectures.

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Extra info for Fine- and Coarse-Grain Reconfigurable Computing

Example text

4 Pleiades The Pleiades processor [28] combines an on-chip microprocessor with an array of heterogeneous programmable computational units of different granularities, which are called satellite processors, connected by a reconfigurable interconnect network. The microprocessor supports the control-intensive components of the applications as well as the reconfiguration, while repetitive and regular data-intensive loops are directly mapped on the array of satellites by configuring the satellite parameters and the interconnections between them.

375 gigabits per second (Gbps). The transceivers are grouped into four-channel transceiver blocks, and are designed for low power 44 K. Tatas et al. consumption and small die size. 2-V logic array with the logic element, interconnect, embedded RAM and DSP blocks offered by the Stratix II family. Stratix II GX devices have somewhat fewer logic resources than the respective Stratix II devices due to the space occupied by the tranceivers. 13-μm, all-layer copper SRAM process, with densities up to 114,140 logic elements (LEs) and up to 10 Mbits of RAM.

The architecture consists of three layers: the routing and logic block (RLB) layer, the routing layer (RL), and the memory layer (ML). The RLB layer is responsible for implementing logic functions and for performing limited routing. Since it is well known that, for practical applications, most nets are short, it is decided to implement in the RLB layer the portion of the routing structure that will be used for routing short nets. The remaining part of the routing structure is implemented in the RL that is formed by connecting multiple switch boxes in a mesh array structure.

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Fine- and Coarse-Grain Reconfigurable Computing by Stamatis Vassiliadis, Dimitrios Soudris, Y. Patt, J. Smith, M. Valero

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