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The other solution, shown at the bottom of the figure, is to make sure that something is driving the output at all times. A third select is generated which drives the output to a good level when neither of the select signals are asserted. 5 Bus Contention Figure 29 Bus Contention - The Problem Figure 30 Bus Contention - The Solution Bus contention occurs when two outputs drive the same signal at the same time as shown in Figure 29. For obvious reasons, this is bad and reduces the reliability of the chip.

Do the I/O signals of the chip meet the timing requirements of the system? The following sections discuss ways of using timing to determine both correct functionality and correct timing. 1 Functional Simulation Functional simulation involves simulating the functionality of a device without taking the timing of the device into account. This type of simulation is important initially in order to get as many bugs out of the device as possible and to determine that the chip will work correctly in your system.

If the result of the tests does not match the 36 Introduction to FPGA Design expected result, the chip signals that there is a problem. The details of what type of tests to run and how to signal a good or bad chip is left up to the designer. 6 Signature Analysis Signature analysis involves putting a pseudo-random sequence of ones and zeroes into the chip and noting the ones and zeroes that come out. This output sequence is referred to as the chip’s signature. This type of testing can be accomplished with the chip in a normal mode of operation, but is usually performed in scan mode as described above.

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Introduction to CPLD and FPGA Design by Zeidman B.

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